Logic
synthesis
Instructor:
Mr. Tran Ngoc Thinh, Ph.D
Department of Computer
Engineering,
Faculty of Computer Science
and Engineering
Ho Chi Minh City University of Technology
268 Ly Thuong Kiet street, Dictrict 10, Ho Chi Minh city, Vietnam.
Phone: (+84)(8) 3864 7256 (Ext. 5843)
Fax: (+84)(8) 864 5137
Email: tnthinh (at) cse (dot) hcmut (dot) edu (dot) vn
Course Description:
• The aim of this course is to
– Present automatic logic synthesis techniques for computer-aided design (CAD) of very large-scale integrated (VLSI) circuits and systems.
– Broadly survey the state of the art, and give a detailed study of various problems, pertaining to the logic-level synthesis of VLSI circuits and systems, including:
• two-level Boolean network optimization,
• multi-level Boolean network optimization,
• technology mapping for library-based designs and field-programmable gate-array (FPGA) designs,
• and state-assignment and re-timing for sequential circuits.
– Cover various representations of Boolean functions, such as binary decision diagrams (BDDs), and discuss their applications in logic synthesis.
Textbook:
[1] Logic Synthesis, Srinivas Devadas, Abhijit Ghosh and Kurt Keutzer, 1994, McGraw Hill.
[2] Synthesis and Optimization of Digital Circuits, G. DeMicheli, 1994, McGraw Hill.
Evaluation: